ST54K - NFC controller and Secure Element single die and a UWB secure, fine-ranging subsystem host,

所有功能

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• • Single die integrating an NFC controller, a secure element and a UWB secure, fine-ranging subsystem host
  • Small, ECOPACK-compliant WLCSP81 package
  • State of-the-art secure element and eSIM Java^® operating system.
• NFC controller
  • Arm^® Cortex^®-M3 mICrocontroller
  • 100% re-flashing capability for firmware update
  • Enhanced active load modulation technology
  • Enhanced TX drive up to 2 W with support of an external 5 V DC/DC converter for TX supply
  • Optimized for extremely small or metal-frame antennas
  • Optimized power consumption modes
  • Ultralow-power Hibernate mode with field detection for low-power mode support
  • Proprietary in-frame synchronization (IFS) in Card Emulation (CE) mode to ensure stability in battery Low and Switched OFF modes
  • System clock:
    • Fractional-N PLL input range of 19.2 to 76.8 MHz
    • 27.12 MHz external crystal oscillator
  • Automatic wakeup via communication interfaces, internal timers, GPIO, RF field or tag detection
• RF communications
  • NFC active and passive Peer-to-Peer mode
    • ISO/IEC 18092 - NFCIP-1 Initiator & Target
  • NFC Reader/Writer mode
    • NFC Forum™ Type 1/2/3/4/5 tags
    • FeliCa™
    • ISO/IEC 15693
    • MIFARE^®
  • NFC Card Emulation mode
    • ISO/IEC 14443 Type A & Type B
    • FeliCa™
    • MIFARE^®
  • Ultra-wideband (UWB) subsystem host control:
    • Car Connectivity Consortium^® (CCC) digital key (DK) phase 3
    • FiRa™ (fine ranging) secure UWB use cases
• External communication interfaces
  • Two master SWP interfaces operating at up to 1.695 Mbit/s
  • Slave I²C interface supporting Standard-mode, Fast-mode, Fast-mode Plus and High-speed mode
  • Master SPI running at up to 8 MHz dedicated to the UWB subsystem
  • Slave SPI interface running at up to 26 MHz
  • ISO/IEC 7816-3 interface
  • General-purpose inputs/outputs (GPIOs)
• Internal communication interfaces
  • CLF/SE SWP digital interface
  • 120 Mbits/s interprocessor communication (IPC) based on a shared internal memory
• Secure microcontroller
  • Arm^® SecurCore^® SC300™ 32-bit RISC core cadenced at 100 MHz
  • Up to 2048 Kbytes of user Flash memory
  • 2 Kbytes of memory cache
  • 64 Kbytes of user RAM
  • Power-saving Standby and Hibernate states
• Secure operating system
  • Supports state-of-the-art secure element operating systems:
    • Java^® Card 3.0.5
    • GlobalPlatform^® 2.3 with Amdts
    • EMVCo™ certification
    • FeliCa™ certification
  • Security-certified according to CC EAL5+
  • Hardware security-enhanced DES & AES accelerators
  • MIFARE Classic cryptography hardware accelerator
  • NESCRYPT coprocessor for public key cryptography algorithms
• Electrical characteristics
  • Battery voltage support from 2.4 V to 5.0 V
  • I/O dedicated voltage level (V_{PS_IO}) from 1.62 V to 3.3 V
  • Supports Class B and Class C operating conditions for external universal integrated-circuit cards (UICCs)
  • Ambient operating temperature −25 to + 85 °C

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